The present invention is directed to semiconductor devices incorporating junctions of varying conductivity types and methods of making such devices. More specifically, the present invention is directed to silicon-on-insulator vertical field-effect transistor devices and methods for fabricating integrated circuits incorporating such devices.
Enhancing semiconductor device performance and increasing device density (the number of devices per unit area) continue to be important objectives of the semiconductor industry. Conventionally, device density is increased by making individual devices smaller and increasing the packing density of the devices, but as feature sizes and design rules decrease, the methods for forming devices and their constituent elements must be adapted. For instance, production device sizes are currently in the range of 0.25 microns to 0.12 micron, with an inexorable trend toward even smaller dimensions. However, as the device dimensions shrink, certain manufacturing limitations arise, especially with respect to the lithographic processes.
Currently most metal-oxide-semiconductor field effect transistors (MOSFETs) are formed in a lateral configuration, with the current flowing parallel to the major plane of the substrate or body surface. As the size of these MOSFET devices decreases to achieve increased device density, the fabrication process becomes increasingly difficult. In particular, the lithographic process for creating the gate region channel is problematic, as the device dimensions approach the wavelength of the radiation used in the lithographic process. For lateral MOSFETs, reductions in the gate length are approaching the point where this dimension cannot be precisely controlled through lithographic techniques. As an alternative, expensive x-ray and electron beam lithographic equipment are being considered for the formation of both MOSFETs and JFETs with state-of-the-art channel lengths.
Generally, integrated circuits comprise a plurality of active devices, including MOSFETs, JFETs and bipolar junction transistors, as well as passive components such as resistors and capacitors. Commonly owned U.S. Pat. Nos. 6,027,975 and 6,197,441, which are hereby incorporated by reference, teach certain techniques for the fabrication of vertical replacement gate (VRG) MOSFETs.
Contemporary silicon-on insulator (SOI processes allow device fabrication on a very thin layer of single crystal silicon on an insulating substrate, rather than on a semiconductor substrate as in conventional integrated circuits. In addition to using silicon dioxide as the insulating layer, two other insulator substances that have the appropriate thermal expansion match to silicon are sapphire and spinel. To form the SOI device, an epitaxial film is grown on the silicon dioxide, or the epitaxial film is deposited on the sapphire or spinel insulating substrate by chemical vapor deposition. In both cases, the resulting typical film thickness is about one micron. The film is patterned and etched using conventional photolithographic techniques to create the islands for each transistor, and the islands are isolated by an insulating trench or by the local oxidation of silicon. Each island may then be processed to form n and p-type source, drain and channel regions by conventional masking and dopant implantation steps.
There are a variety of other techniques for growing single crystal silicon on a silicon dioxide surface. For example, the silicon dioxide layer can be formed beneath the surface of a silicon wafer by high-dose oxygen implantation. The thin silicon layer remaining on the surface above the implanted silicon dioxide is usually about 0.1 xcexcm thick, and can be used as the thin film for device fabrication. This process is referred to as separation by implantation of oxygen (SIMOX). If needed, a thicker silicon film can be grown epitaxially on the SIMOX wafer, using the thin silicon crystalline layer as a seed for the epitaxial layer.
Devices fabricated with SOI technology have several advantages over conventional MOSFET devices. Since the silicon film is thin, the doped regions extend through the film to the insulating substrate (e.g., the sapphire, spinel or silicon dioxide), thereby reducing the junction capacitance to a very small value associated only with the sidewalls between the source/drain/channel regions. Also, since the metal interconnections between transistors pass over the insulating substrate, i.e., in regions where there is no epitaxial silicon, the typical interconnect-substrate capacitance is eliminated, as well as the parasitically induced channels between transistor devices. These capacitance reductions improve the high-frequency performance of the SOI devices over conventional devices formed in a silicon substrate. Also, when implemented in CMOS technology, the SOI structure eliminates the induced latch-up problems because there is no p-n-p-n thyristor between the power supply and ground. The leakage of current from the active regions to the substrate is also significantly reduced in SOI devices because the substrate is an insulator. Further advantages of the SOI technology include resistance to short-channel effects, steeper subthreshold slopes, increased current drive and generally similar processing steps.
MOSFETs fabricated with SOI technology include non-fully depleted MOSFETs where the width of the silicon film is greater than the maximum channel depletion width and fully-depleted MOSFETs having a silicon film thickness that is less than the maximum channel region width. Unlike bulk silicon MOSFETs, the substrate of the prior art SOI MOSFET is usually electrically floating. Therefore, in a non-fully depleted MOSFET, carriers (holes in an NMOS device and electrons in a PMOS device) generated by impact ionization accumulate near the source/body junction of the MOSFET. Eventually sufficient carriers will accumulate to forward bias the body with respect to the source, thus lowering the threshold voltage due to the body-bias effect. Extra current will start flowing, resulting in a xe2x80x9ckinkxe2x80x9d in the current/voltage characteristics. This reduces the achievable gain and dynamic swing for SOI devices fabricated for analog circuits and gives rise to an abnormality in the device transfer characteristics for digital circuit SOI MOSFETs.
In a fully-depleted SOI MOSFET, the channel is completely depleted under normal operating conditions. The source-channel junction has a lower potential barrier to the carriers generated by impact ionization and thus there is a reduced effect on the body and channel potential, and the xe2x80x9ckinkxe2x80x9d is reduced. However, the resulting output resistance is poor, thus making SOI technology less attractive than conventional bulk technology for analog circuitry. Further, in a fully-depleted MOSFET, the depletion charge is reduced for a given body doping concentration, leading to a smaller threshold voltage. But the threshold voltage is sensitive to variations in the silicon film thickness, which makes the fabrication of high performance circuits difficult. Also, the thin silicon film thickness causes high source/drain series resistances, lowering device operational speed. These conditions are substantially due to the lack of a grounded body substrate.
To provide further advances in the fabrication of MOSFETs, an architecture and a fabrication process is provided for a vertical SOI MOSFET device.
According to one embodiment of the invention, a semiconductor device includes a substrate with a first layer of semiconductor material and at least three insulator layers formed thereover. A window or trench formed in the three layers comprises a relatively thin polycrystalline silicon layer around the inner wall surface thereof and an insulator material in the remaining window volume. The source, drain and channel regions are formed in the polycrystalline silicon layer. In a preferred embodiment, the first and the third insulating layers serve as dopant sources to form the source and drain regions and the second insulator layer is a sacrificial layer that is removed and replaced with gate oxide and a gate. In another embodiment, insulator material is absent from the back side of the polycrystalline silicon layer where the channel region is formed, but is present on the backside of the source and drain regions. Thus the backside of the polycrystalline silicon layer in the region of the channel can be contacted and thus grounded, similar to the grounding of the substrate in a conventional lateral MOSFET.
In an associated method of manufacture, an integrated circuit structure is fabricated by providing multiple parallel semiconductor layers in which a window is formed. According to one embodiment, a relatively thin polycrystalline silicon layer is formed around the interior circumference of the window and the source, drain and channel regions are formed therein. The remainder of the window is filled with an insulator material. Certain of the multiple parallel semiconductor layers serve as dopant sources as the source, drain and channel regions are formed by solid phase diffusion of the dopant therefrom. In fabricating the vertical SOI MOSFET, the gate length is precisely controlled through the removal of a sacrificial layer among the multiple parallel layers.